ACS709
High Bandwidth, Fast Fault Response Current Sensor IC
In Thermally Enhanced Package
Functional Description
Overcurrent Fault Operation
The primary concern with high-speed fault detection is that noise
may cause false tripping. Various applications have or need to
be able to ignore certain faults that are due to switching noise
or other parasitic phenomena, which are application dependant.
The problem with simply trying to filter out this noise up front is
that in high-speed applications, with asymmetric noise, the act of
filtering introduces an error into the measurement. To get around
this issue, and allow the user to prevent the fault signal from
being latched by noise, a circuit was designed to slew the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin voltage based on the value of the capacitor from that pin to
ground. Once the voltage on the pin falls below 2 V, as estab-
lished by an internal reference, the fault output is latched and
pulled to ground quickly with an internal N-channel MOSFET.
Fault Walk-through
The following walk-through references various sections and
2. When the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin voltage reaches approximately 2 V, the
fault is latched, and an internal NMOS device pulls the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin voltage to approximately 0 V. The rate at which the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ
pin slews downward (see [4] in the figure) is dependent on the
external capacitor, C OC , on the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
3.When the FAULT_EN pin is brought low, the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin starts
resetting if no OC Fault condition exists. The internal NMOS
pull-down turns off and an internal PMOS pull-up turns on (see
[7] if the OC Fault condition still exists).
4. The slope, and thus the delay, on the fault is controlled by the
capacitor, C OC , placed on the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin to ground. During this
portion of the fault (when the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin is between V CC and
2 V), there is a 3 mA constant current sink, which discharges
C OC . The length of the fault delay, t, is equal to :
C OC ( V CC – 2 V )
attributes in the figure below.This figure shows different
fault set/reset scenarios and how they relate to the voltages on
the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin, FAULT_EN pin, and the internal Overcurrent
(OC) Fault node, which is invisible to the customer.
t =
3 mA
where V CC is the device power supply voltage.
(1)
1.Because the device is enabled (FAULT_EN is high for a mini-
mum period of time, the Fault Enable Delay, t FED , 15 μ s typical)
and there is an OC fault condition, the device ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin starts
discharging.
5. The ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin did not reach the 2 V latch point before the
OC fault condition cleared. Because of this, the fixed 3 mA
current sink turns off, and the internal PMOS pull-up turns on to
recharge C OC through the ˉF ˉAˉ ˉUˉ ˉLˉ ˉTˉ pin.
V CC
1
1
1
FAULT
(Output)
2V
4
2
6
t FED
4
5
6
4
2
6
8
4
2
7
3
0V
FAULT_EN
(Input)
OC Fault
Condition
(Active High)
Time
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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